MRAM Device and Fabrication Method Thereof

ABSTRACT

According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

BACKGROUND

Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor memory device involves spin electronics, which combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, rather than the charge of the electrons, are used to indicate a bit.

One such spin electronic device is magnetoresistive random access memory (MRAM) array, which includes conductive lines (word lines and bit lines) positioned in different directions, e.g., perpendicular to each other in different metal layers. The conductive lines sandwich a magnetic tunnel junction (MTJ), which functions as a magnetic memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 9 are a first embodiment to form an MRAM device;

FIGS. 10 through 14 are a second embodiment to form an MRAM device; and

FIG. 15 is a MRAM array comprising structures of embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Embodiments will be described with respect to a specific context, namely magnetoresistive random access memory (MRAM) devices. Other embodiments may also be applied, however, to other semiconductor structures.

FIGS. 1 through 9 illustrate a first embodiment to form an MRAM device. FIG. 1 shows a cross-section view of a structure during manufacture of an MRAM device. FIG. 1 illustrates a substrate 10. The substrate 10 includes an inter-metal dielectric (IMD) layer 12 with a metallization pattern 14. The IMD layer 12 may be an extra low-k dielectric (ELK) layer, such as carbon doped silicon dioxide, may be an oxide, such as silicon oxide, and/or may be the like or a combination thereof. The metallization pattern 14 may be copper, aluminum, the like, and/or a combination thereof. The substrate may also include active and passive devices, for example, underlying the IMD layer 12. These further components are omitted from the figures for clarity, and how these components are formed will be readily apparent to a person having ordinary skill in the art.

FIG. 1 further shows a first dielectric layer 16 formed over the substrate 10 and a second dielectric layer 18 formed over the first dielectric layer 16. In other embodiments, only one dielectric layer is used, or further dielectric layers are used. The first dielectric layer 16 in this example is silicon carbide (SiC). In other embodiments, the first dielectric layer 16 may be silicon oxynitride (SiON), the like, and/or a combination thereof. The second dielectric layer 18 is silicon nitride (SiN) in this embodiment. In other embodiments, the second dielectric layer 18 may be silicon dioxide (SiO₂), the like, and/or a combination thereof. Further, the first dielectric layer 16 and the second dielectric layer 18 may be the same or different materials and/or compositions. Each of the first dielectric layer 16 and the second dielectric layer 18 may be formed by acceptable deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, and/or a combination thereof.

An opening 20 is formed through the first dielectric layer 16 and the second dielectric layer 18 to expose a portion of the metallization pattern 14. The opening may be formed using acceptable lithography techniques, such as by an anisotropic etch.

FIG. 2 illustrates the formation of a bottom electrode layer 24, a magnetic tunnel junction (MTJ) layer(s) 26, a first top electrode layer 28, and a second top electrode layer 30. Each layer is formed conformally over the substrate 10, such as over the second dielectric layer 18 and within and along sidewalls of the opening 20. The layers are also formed sequentially. The bottom electrode layer 24 is formed over the second dielectric layer 18. Then, the MTJ layer(s) 26 is formed over the bottom electrode layer 24, and next, the first top electrode layer 28 is formed followed by the formation of the second top electrode layer 30. Each of the bottom electrode layer 24, the first top electrode layer 28, and the second top electrode layer 30 may be copper, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and/or a combination thereof. Each of the bottom electrode layer 24, the first top electrode layer 28, and the second top electrode layer 30 may be formed by CVD, PVD, ALD, the like, and/or a combination thereof. It is worth noting that only one top electrode layer or more than two top electrode layers may be used, and the use of two in this embodiment is merely as an example. Further, the two top electrode layers 28 and 30 may be the same or different materials and/or compositions.

The MTJ layer(s) 26 may include various layers formed of different combinations of materials. In an exemplary embodiment, MTJ layer(s) 26 include a pinning layer, a tunnel barrier layer, and a free layer. In addition, MTJ layer(s) 26 may have other variations including other layers, such as anti-ferro-magnetic layers. In an exemplary embodiment, the pinning layer is formed of PtMn, tunnel barrier layer is formed of MgO, and free layer is formed of CoFeB. The magnetic moment of free layer may be programmed causing the resistance of the resulting MTJ cell to be changed between a high resistance and a low resistance. It is realized that MTJ layer(s) 26 may have many variations, which are also within the scope of the present disclosure.

In FIG. 3, the MTJ layer(s) 26, the first top electrode layer 28, and the second top electrode layer 30 are etched to form a MTJ 32, a first top electrode 34, and a second top electrode 36, such as in a stack. The MTJ 32, first top electrode 34, and second top electrode 36 form part of a MRAM device. The layers may be etched using acceptable photolithography techniques. A spacer layer 38 is formed over the exposed portions of the bottom electrode layer 24, over sidewalls of the MTJ 32, first top electrode 34, and second top electrode 36, and over the second top electrode 36. The spacer layer 38 in this example is SiN, but in other embodiments may be SiC, SiON, silicon oxycarbide (SiOC), the like, and/or a combination thereof. The spacer layer 38 may be formed using CVD, PVD, ALD, the like, and/or a combination thereof.

In FIG. 4, an anti-reflective coating (ARC) layer 40 is formed over the spacer layer 38. The ARC layer 40 in this example is a bottom ARC layer and is an organic material, such as C_(x)H_(x)O_(x). The ARC layer 40 may also be silicon oxynitride, silicon nitride, the like, and/or a combination thereof. The ARC layer 40 may be formed using CVD, ALD, PVD, the like, and/or a combination thereof.

FIG. 5 shows the structure after planarization and etch-back. The ARC layer 40 and portions of the spacer layer 38 are removed, for example, by a chemical mechanical polish (CMP) followed by an etch-back selective to the materials of the ARC layer 40 and the spacer layer 38. The CMP may polish the ARC layer 40 and the spacer layer 38 to a top surface of the second top electrode 36. Then, the etch-back may etch the remaining ARC layer 40 and portions of the spacer layer 38 to a height less than the height of the second top electrode 36 such that the second top electrode 36 protrudes from the resulting buffer 42. The buffer 42 may have a top surface that is higher than an interface between the MTJ 32 and the first top electrode 34, and in this example, the buffer 42 has a top surface that is higher than an interface between the first top electrode 34 and the second top electrode 36. It is worth noting that the planarization may be by any combination of CMP, etching, or the like. For example, only an etch-back is used in another embodiment.

FIG. 6 depicts the formation of a capping layer 44, which may also act as an etch stop layer, over the buffer 42 and the second top electrode 36. In this embodiment, the capping layer 44 is SiC, but in other embodiments, the capping layer 44 may be SiC, SiN, SiON, the like, and/or a combination thereof. The capping layer 44 may be formed by CVD, PVD, ALD, the like, and/or a combination thereof.

In FIG. 7, lateral portions 46 of the capping layer 44, the buffer 42, the bottom electrode layer 24, and the second dielectric layer 18 are etched to the first dielectric layer 16. This etching removes portions of the bottom electrode layer 24 that would otherwise form an electrical connection between other MRAM cells within an array. The etching results in individual MRAM cells. The etching may be performed by acceptable photolithography technique, such as by using an anisotropic etch.

FIG. 8 shows the further formation of the capping layer 44 by forming sidewall capping portions 52 and the formation of an overlying dielectric layer 48. The sidewall capping portions 52 are formed in the in the areas of the removed lateral portions 46. The formation of the sidewall capping portions may be by CVD, ALD, PVD, the like, and/or a combination thereof. In this embodiment, the sidewall capping portions 52 are the same material as the capping layer 44, and as such, the formation of the sidewall capping portions 52 may cause the capping layer 44 to become thicker. In other embodiments, if the sidewall capping portions 52 are a different material, the sidewall capping portions 52 may form a different layer over the capping layer 44. The overlying dielectric layer 48 is formed over the sidewall capping portions 52 and the capping layer 44 and may be an inter-layer dielectric (ILD) layer or an IMD layer. The overlying dielectric layer 48 may be an extra low-k dielectric (ELK) layer, such as carbon doped silicon dioxide, may be an oxide, such as silicon oxide, and/or may be the like or a combination thereof. The overlying dielectric layer 48 may be formed using CVD, PVD, ALD, the like, and/or a combination thereof. After being deposited, the overlying dielectric layer 48 may be planarized, such as by CMP.

In FIG. 9, an opening is etched through the overlying dielectric layer 48 and the capping layer 44 to the second top electrode 36. The opening may be etched using an acceptable photolithography technique, such as a single or dual damascene process. A conductive material 50 is formed in the opening and includes a metallization pattern portion and a via portion between the metallization pattern portion and the second top electrode 36. The conductive material 50, such as a metal and alloys, may be deposited in the opening to form a via and a metallization. A thin barrier layer 54 may also be deposited between the conductive material and the overlying dielectric layer 48. The details for forming the metallization and via are well known in the art, and as such, are omitted herein for brevity.

FIGS. 10 through 14 illustrate a second embodiment to form an MRAM device. The structure of FIG. 10 is first processed through the steps discussed with respect to FIGS. 1 through 3. In FIG. 10, the spacer layer 38 is etched to form a spacer 60. A portion 62 of the spacer layer 38 may remain in the opening 20. The etching may be by an anisotropic etch using acceptable photolithography techniques. A portion of the spacer 60 directly adjoins the MTJ 32, the first top electrode 34, and part of the second top electrode 36. In other embodiments, the spacer 60 has a height in a part that directly adjoins the MTJ 32 that is greater than a height of the MTJ 32 or has a height that is above the interface of the MTJ 32 and the first top electrode 34. A portion of the second top electrode 36 is exposed from the spacers 60. In this embodiment, the spacer 60 is formed around and encloses the MTJ 32. In other embodiments, separate spacers may be formed at various parts along the MTJ 32 and may not fully enclose the MTJ 32.

In FIG. 11, a capping layer 64 is formed over the second top electrode 36 and the spacer 60 similar to the capping layer 44 in FIG. 6. In FIG. 12, lateral portions 66 of the capping layer 64, the bottom electrode layer 24, and the second dielectric layer 18 are etched to the first dielectric layer 16, similar to what is performed in FIG. 7. In FIG. 13, sidewall capping portions 70 and an overlying dielectric layer 68 is formed similarly to the sidewall capping portions 52 and the overlying dielectric layer 48 in FIG. 8. In FIG. 14, the opening is formed in the overlying dielectric layer 68, and the thin barrier layer 54 and conductive material 50 are formed in the opening, similar to FIG. 9.

FIG. 15 illustrates a MRAM array 100 comprising structures of embodiments. MTJ cells 102, such as the stacks of the MTJ 32, the first top electrode 34, and the second top electrode 36, are arranged as array 100 having columns and rows. Each of the MTJ cells 102 is connected between one of the bit lines BL (referred to as BL0, BL1, . . . and the like) and one of the source lines SL (referred to as SL0, SL1, . . . and the like). Select transistor 104 is controlled by one of word lines WL (referred to as WL0, WL1, . . . and the like). The write currents of MTJ cells 102 are applied between the bit lines BL and the source lines SL. Word lines WL also control which one of the MTJ cells 102 is operated.

Embodiments may realize advantages. First, by having a buffer 42 or a spacer 60, an overlay window may be increased and MTJ program failure can be avoided. Further, the buffer 42 or spacer 60 may increase the strength and protection of the MTJ sidewall. Also, the process may be simplified, such as the process to form the top electrode and by reducing the number of layers formed for the structure.

According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

Another embodiment a MRAM device. The MRAM device comprises a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) over the bottom electrode, a top electrode over and having an interface with the MTJ, a dielectric material along a sidewall of the MTJ, a dielectric layer over the top surface of the top electrode and the dielectric material, and a via extending through the dielectric layer to the top electrode. The dielectric material has a height greater than the interface of the top electrode and the MTJ and less than a top surface of the top electrode.

A further embodiment is a method for forming a MRAM device. The method comprises forming a bottom electrode layer on a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; forming a top electrode layer over the MTJ layers; removing portions of the MTJ layers and the top electrode layer to form a stack; forming a first dielectric layer over the stack; and removing a portion of the first dielectric layer. The stack comprises remaining portions of the MTJ layers and the top electrode layer, and the stack has a sidewall. A remaining portion of the first dielectric layer adjoins the sidewall of the stack, and the remaining portion of the first dielectric layer has a height above a thickness of the MTJ layers and below a thickness of the stack.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

1. A magnetoresistive random access memory (MRAM) device comprising: a bottom electrode over a substrate; a stack over the bottom electrode, the stack comprising a magnetic tunnel junction (MTJ) and a top electrode; a dielectric material along a sidewall of the stack, the dielectric material having a height greater than a thickness of the MTJ and less than a stack height; a dielectric layer over the stack and the dielectric material; and a conductive material extending through the dielectric layer to the top electrode of the stack.
 2. The MRAM device of claim 1, wherein the dielectric material comprises a planarized top surface at the height.
 3. The MRAM device of claim 1, wherein the dielectric material is a spacer along the sidewall.
 4. The MRAM device of claim 1 further comprising a capping layer over the stack and the dielectric material, the dielectric layer being over the capping layer.
 5. The MRAM device of claim 4, wherein the capping layer adjoins a top surface of the bottom electrode and sidewalls of the bottom electrode.
 6. The MRAM device of claim 4, wherein the capping layer adjoins the bottom electrode at only sidewalls of the bottom electrode.
 7. The MRAM device of claim 1, wherein the top electrode comprises a first top electrode and a second top electrode over the first top electrode, the first top electrode comprising a material different from the second top electrode.
 8. The MRAM device of claim 1, wherein the bottom electrode is electrically coupled to a conductive pattern in the substrate.
 9. The MRAM device of claim 1, wherein the conductive material is in a via extending to the top electrode.
 10. A magnetoresistive random access memory (MRAM) device comprising: a bottom electrode over a substrate; a magnetic tunnel junction (MTJ) over the bottom electrode; a top electrode over and having an interface with the MTJ; a dielectric material along a sidewall of the MTJ, the dielectric material having a height greater than the interface of the top electrode and the MTJ and less than a top surface of the top electrode; a dielectric layer over the top surface of the top electrode and the dielectric material; and a via extending through the dielectric layer to the top electrode.
 11. The MRAM device of claim 10, wherein the dielectric material comprises a planarized top surface at the height.
 12. The MRAM device of claim 10, wherein the dielectric material is a spacer along the sidewall.
 13. The MRAM device of claim 10 further comprising a capping layer over the top surface of the top electrode and over the dielectric material, the dielectric layer being over the capping layer, the capping layer adjoining a top surface of the bottom electrode.
 14. The MRAM device of claim 10 further comprising a capping layer over the top surface of the top electrode and over the dielectric material, the dielectric layer being over the capping layer, the capping layer adjoining the bottom electrode at sidewalls of the bottom electrode and not adjoining the bottom electrode at an upper surface of the bottom electrode.
 15. A method for forming a magnetoresistive random access memory (MRAM) device, the method comprising: forming a bottom electrode layer on a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; forming a top electrode layer over the MTJ layers; removing portions of the MTJ layers and the top electrode layer to form a stack, the stack comprising remaining portions of the MTJ layers and the top electrode layer, the stack having a sidewall; forming a first dielectric layer over the stack; and removing a portion of the first dielectric layer, a remaining portion of the first dielectric layer adjoining the sidewall of the stack, the remaining portion of the first dielectric layer having a height above a thickness of the MTJ layers and below a thickness of the stack.
 16. The method of claim 15, wherein the removing the portion of the first dielectric layer comprises planarizing the first dielectric layer to the height.
 17. The method of claim 15, wherein the removing the portion of the first dielectric layer comprises etching the first dielectric layer to form a spacer adjoining the sidewall of the stack, the portion of the first dielectric layer being laterally disposed from the spacer.
 18. The method of claim 15, wherein forming the top electrode layer comprises forming a first top electrode layer and a second top electrode layer over the first top electrode layer, the second top electrode layer comprising a material different from the top electrode layer.
 19. The method of claim 15 further comprising forming a capping layer over the stack and the remaining portion of the first dielectric layer.
 20. The method of claim 15 further comprising: forming a second dielectric layer over the remaining portion of the first dielectric layer and the stack; etching an opening through the second dielectric layer to the top electrode layer of the stack; and forming a conductive material in the opening. 